1. Field of the Invention
The present invention relates to a bidirectional bus driver which drives an internal bidirectional bus of a semiconductor integrated circuit and a bidirectional bus circuit including bidirectional buses and the bidirectional bus driver.
2. Description of the Related Art
A conventional bidirectional signal control circuit is disclosed, for example, in Japanese Patent Publication Kokai (Laid-Open) No. 2001-102914. FIG. 7 is a schematic circuit diagram showing the structure of the conventional bidirectional signal control circuit. In the circuit shown in FIG. 7, a bidirectional bus N140 is driven by multiple tristate buffer circuits 112, 122, and 132, each disposed in separate circuit blocks 110, 120, and 130. These circuit blocks 110, 120, and 130 receive a data signal from the bidirectional bus N140, through receiver circuits 111, 121, and 131 disposed in the respective circuit blocks.
A conventional bidirectional bus repeater is disclosed, for example, in U.S. Pat. No. 5,202,593. FIG. 8 is a schematic circuit diagram showing the structure of the conventional bidirectional bus repeater. FIG. 9 is a timing chart illustrating the operation of the bidirectional bus repeater shown in FIG. 8. If external bus drivers (not shown) connected to buses 212 and 214 in the circuit shown in FIG. 8 do not pull the buses to a low logic level, the supply voltage across resistors included in buffers 216 and 218 causes the buses 212 and 214 to be pulled up, consequently bringing signals A and B to a high logic level (t11 in FIG. 9). Meanwhile, control signals BD and AD output from three-input NOR gates 224 and 226 are low, and control signals AU and BU output from single-shot devices 220 and 222 are low (t11 in FIG. 9).
When an external bus driver (not shown) connected to the bus 214 pulls the bus to a low logic level, bringing the signal A to a low logic level, the control signal BD output from the three-input NOR gate 224 is brought to a high logic level, and the buffer 218 brings the signal B in the bus 212 to a low logic level (t12 in FIG. 9). Even after this high-to-low transition in the signal B in the bus 212, the control signal AD remains low because the control signal BD supplied to the three-input NOR gate 226 is high (t12 in FIG. 9).
When an external bus driver (not shown) connected to the bus 214 pulls the bus to a high logic level or does not pull the bus to a low logic level, the control signal BD output from the three-input NOR gate 224 is brought to a low logic level (t21 in FIG. 9). The falling edge of the control signal BD triggers a single-shot device 222 to generate a high level pulse as the control signal BU, and the buffer 218 immediately brings the signal B in the bus 212 to a high logic level (t21 in FIG. 9).
The conventional bidirectional signal control circuit shown in FIG. 7 has the following problem. As the semiconductor integrated circuits of succeeding generations have finer design rules, the pitches of wiring for connecting logic gates have become narrow and are becoming smaller than the wiring height. In fine wiring, the coupling capacitance between adjacent wires is larger than the coupling capacitance between adjacent wiring layers. As the cross-sectional area of wiring shrinks, the wiring resistance per unit length increases. Consequently, a long wire such as the bus N140 shown in FIG. 7 develops a delay due to wiring capacitance and wiring resistance, obstructing high-speed signal transfer.
The conventional bidirectional bus repeater shown in FIG. 8 has another problem. When a low-to-high transition occurs in the signal A of the bus 214 (waveform al in FIG. 9), the three-input NOR gate 224 brings the control signal BD to a low logic level (waveform a2 in FIG. 9). The falling edge of the control signal BD triggers a single-shot device 222 to generate a high level pulse as the control signal BU high (waveform a3 in FIG. 9). As the waveform a3 in FIG. 9 indicates, the rise of the control signal BU by a single-shot device 222 may occur a little later than the fall of the control signal BD by the three-input NOR gate 224. If this delay occurs, the three inputs B, BD, and BU of the three-input NOR gate 226 are kept low for a period between the fall of the control signal BD (t31 in FIG. 9) and the rise of the control signal BU (t32 in FIG. 9) (the period between t31 and t32 is magnified in FIG. 9), bringing the control signal AD output from the three-input NOR gate 226 to a high logic level (a4 in FIG. 9) for a brief moment. Meanwhile, the buffer 216 pulls down the signal A of the bus 214 (a5 in FIG. 9) for a brief moment. When an external bus driver (not shown) connected to the bus 214 does not pull the bus to a low logic level and when the pull-up resistor of the buffer 216 pulls up the bus 214, an oscillation occurs, and the circuit operation becomes unstable. If an external bus driver (not shown) connected to the bus 214 pulls the bus to a high logic level, a large current momentarily flows from the external bus driver (not shown) to the buffer 216. This will impair the reliability of the wiring.